Method of manufacturing semiconductor device

ABSTRACT

To provide a semiconductor device capable of having improved adhesion between a plating film and a wiring layer. A method of manufacturing the semiconductor device includes a step of forming a wiring layer having a surface covered with an oxide film, a step of removing a portion of the oxide film by dry etching to form, in the oxide film, a first opening f exposing a portion of the wiring layer, a step of forming a passivation film covering the wiring layer, is provided with a second opening communicated with the first opening, and is made of an insulating resin material, and a step of growing a plating film on the wiring layer exposed from the first and second openings.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2017-149953 filed onAug. 2, 2017 including the specification, drawings, and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a method of manufacturing asemiconductor device.

The semiconductor device described in Japanese Unexamined PatentApplication Publication No. 2017-69412 (Patent Document 1) hasconventionally be known. The semiconductor device described in PatentDocument 1 has a semiconductor substrate, a wiring layer, a passivationfilm, and a plating film. The wiring layer is placed on thesemiconductor substrate. The wiring layer contains aluminum (Al). Thepassivation film is placed to cover the wiring layer therewith. Thepassivation film is provided with an opening. The passivation film ismade of an insulating resin material. From the opening, the wiring layeris exposed. The plating film is placed on the wiring layer exposed fromthe opening.

In the manufacturing steps of the semiconductor device described inPatent Document 1, firstly, the wiring layer is formed. Secondly, thepassivation film is formed. Thirdly, the plating film is grown on thewiring layer exposed from the opening provided in the passivation film.

PATENT DOCUMENT

[Patent Document 1] Japanese Unexamined Patent Application PublicationNo. 2017-69412

SUMMARY

A wiring layer is formed by patterning a material configuring the wiringlayer formed by sputtering or the like by photolithography and etching.A photoresist used for photolithography is removed by ashing. Duringashing, the surface of the wiring layer is oxidized. The wiring layerhas therefore a surface covered with the resulting oxide film.

This oxide film becomes an obstacle to the growth of a plating film onthe wiring layer. As one method for removing this oxide film, dryetching of the oxide film via an opening provided in the passivationfilm can be considered. During such dry etching, however, carbon derivedfrom the passivation film may be redeposited onto the wiring layer. Thecarbon which has been redeposited onto the wiring layer becomes anobstacle for the growth of a plating film on the wiring layer.

Presence of the obstacle to the growth of a plating film may result ininsufficient adhesion between the wiring layer and the plating film andinsufficient adhesion between the wiring layer and the plating film maycause separation of the plating film from the wiring layer during wirebonding or the like to the plating film.

The other problems and novel features will be apparent from thedescription herein and accompanying drawings.

A method of manufacturing a semiconductor device according to oneembodiment includes a step of forming a wiring layer, a step of forminga first opening, a step of forming a passivation film, and a step ofcausing the growth of a plating film. In the forming wiring layer, awiring layer having a surface covered with an oxide film is formed on asemiconductor substrate. In the forming first-opening, a portion of theoxide film is removed by dry etching to form, in the oxide film, a firstopening for exposing therefrom a portion of the wiring layer. In theforming passivation film, a passivation film is formed which covers thewiring layer, is provided with a second opening communicated with thefirst opening, is and made of an insulating resin material. In theplating film growth step, a plating film is grown on the wiring layerexposed from the first opening and the second opening.

The method of manufacturing a semiconductor device according to the oneembodiment can improve adhesion between the plating film and the wiringlayer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a semiconductor device of First Embodiment;

FIG. 2 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below a source pad;

FIG. 3 is an enlarged cross-sectional view of FIG. 2;

FIG. 4 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below a gate pad;

FIG. 5 is an enlarged cross-sectional view of FIG. 4;

FIG. 6 is a flow chart showing manufacturing steps of the semiconductordevice of First Embodiment;

FIG. 7 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the source pad in a front end step;

FIG. 8 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the gate pad in the front end step;

FIG. 9 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the source pad in a forming interlayer insulatingfilm;

FIG. 10 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the gate pad in the forming interlayer insulatingfilm;

FIG. 11 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the source pad in a forming contact plug;

FIG. 12 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the gate pad in the forming contact plug;

FIG. 13 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the source pad in a forming wiring layer;

FIG. 14 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the gate pad in the forming wiring layer;

FIG. 15 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the source pad in a forming first passivationfilm;

FIG. 16 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the gate pad in the forming first passivationfilm;

FIG. 17 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the source pad in a forming first opening;

FIG. 18 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the gate pad in the forming first opening;

FIG. 19 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the source pad in a forming second opening;

FIG. 20 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the gate pad in the forming second opening;

FIG. 21 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the source pad in a forming second passivationfilm;

FIG. 22 is a cross-sectional view of the semiconductor device of FirstEmbodiment right below the gate pad in the forming second passivationfilm;

FIG. 23 is a graph showing crystal orientation at the surface of thewiring layer of the semiconductor device of First Embodiment; and

FIG. 24 is a graph showing crystal orientation at the surface of thewiring layer of a semiconductor device of Second Embodiment.

DETAILED DESCRIPTION

Embodiments will be described in detail referring to some drawings. Inthe drawings shown below, the same portions or portions correspondingthereto will be identified by the same reference numerals andoverlapping descriptions will be omitted.

First Embodiment

The configuration of a semiconductor device of First Embodiment willhereinafter be described.

The semiconductor device of First Embodiment is, for example, a trenchgate type power MOSFET (metal oxide semiconductor field effecttransistor). The semiconductor device of First Embodiment is not limitedthereto. The semiconductor device of First Embodiment may be a planargate type power MOSFET. The semiconductor device of First Embodiment mayalso be an IGBT (insulated gate bipolar transistor).

As shown in FIG. 1, the semiconductor device of First Embodiment has agate pad GP and a source pad SP. As shown in FIGS. 2 and 3, thesemiconductor device of First Embodiment has a semiconductor substrateSUB, a gate insulating film GO, a gate electrode GE, an interlayerinsulating film ILS, a contact plug CP, a wiring layer WL1, a wiringlayer WL2, a first passivation film PV1, a second passivation film PV2,a plating film PL1, and a plating film PL2.

The semiconductor substrate SUB is made of, for example, a silicon (Si)single crystal. The semiconductor substrate SUB has a first surface FSand a second surface SS. The second surface SS is a surface opposite tothe first surface FS.

The semiconductor substrate SUB has a source region SR, a drain regionDRA, a drift region DRI, and a body region BR. The source region SR isplaced in the first surface FS. The drain region DRA is placed in thesecond surface SS. The drift region DRI is placed on the first surfaceFS side of the drain region DRA. The body region BR is sandwichedbetween the drain region DRA and the source region SR.

The first surface FS has therein a trench TR. The trench TR extends fromthe first surface FS toward the second surface SS. The trench TR extendsto reach the drift region DRI. From another point of view, the sourceregion SR, the body region BR, and the drift region DRI are exposed fromthe side wall of the trench TR.

The source region SR, the drain region DRA, and the drift region DRIeach have a first conductivity type. The body region BR has a secondconductivity type. The second conductivity type is a conductivity typeopposite to the first conductivity type. For example, when the firstconductivity type is an n type, the second conductivity type is a ptype.

The trench TR has, on the side wall and bottom wall thereof, a gateinsulating film GO. The gate insulating film GO is made of, for example,silicon dioxide (SiO₂). The trench TR has therein a gate electrode GE.More specifically, the gate insulating film GO is sandwiched between thegate electrode GE and the side wall and bottom wall of the trench TR.From another point of view, the gate electrode GE faces with the bodyregion BR (the body region BR exposed from the side wall of the trenchTR) sandwiched between the source region SR and the drift region DRI,while being insulated by the gate insulating film GO. The gate electrodeGE is made of, for example, impurity-doped polycrystalline Si.

The source region SR, the body region BR, the drift region DRI, thedrain region DRA, the gate insulating film GO, and the gate electrode GEconfigure a trench gate type MOSFET.

The interlayer insulating film ILD is placed on the first surface FS.The interlayer insulating film ILD is made of, for example, SiO₂. Theinterlayer insulating film ILD has therein a contact hole CH. The sourceregion SR is exposed from the interlayer insulating film ILD via thecontact hole CH.

The contact plug CP is placed in the interlayer insulating film ILD.More specifically, the contact plug CP is buried in the contact hole CH.The contact plug CP is made of, for example, tungsten (W). The contactplug CP is, at one end thereof, electrically coupled to the sourceregion SR. The contact plug CP is, at the other end thereof,electrically coupled to the wiring layer WL1. The other end of thecontact plug CP has, in the vicinity of the center thereof, a portionrecessed toward the side of the one end. Although not illustrated, thewiring layer WL2 and the gate electrode GE are electrically coupled toeach other via the contact plug CP.

The wiring layer WL1 is a source wiring. The wiring layer WL1 is placedon the interlayer insulating film ILD. The wiring layer WL1 preferablycontains Al. The wiring layer WL1 is made of Al or an Al alloy. The Alalloy configuring the wiring layer WL1 is, for example, an AlCu alloy.Alternatively, the Al alloy configuring the wiring layer WL1 may be anAlSi alloy or AlSiCu alloy.

The wiring layer WL1 has a surface covered with an oxide film OX. Theterm “surface of the wiring layer WL1” as used herein means the surfaceof the wiring layer WL1 on the side opposite to the interlayerinsulating film ILD. The oxide film OX is an oxide of a materialconfiguring the wiring layer WL1. When the wiring layer WL1 contains Al,the oxide film OX is made of an oxide of Al. The oxide film OX has anopening OP1. The wiring layer WL1 is exposed from the oxide film OX viathe opening OP1.

The wiring layer WL1 is, for example, a sputter film. The sputter filmis a film formed by sputtering. The wiring layer WL1 has a thickness T.The thickness T is preferably 1 μm or more.

In crystal grains at the surface of the wiring layer WL1, a proportionof those having crystal orientation deviated by 5° or less from the<111> plane is preferably 40% or more. The deviation from the <111>plane is determined from the angle made by the normal direction of thecrystal plane of the crystal grains at the surface of the wiring layerWL1 and the normal direction of the <111> plane of the crystal grains.The crystal orientation of the crystal grains at the surface of thewiring layer WL1 is measured using X-ray diffraction.

The first passivation film PV1 is placed to cover the wiring layer WL1therewith. The first passivation film PV1 is made of an insulatinginorganic material. The first passivation film PV1 is made of, forexample, silicon oxynitride (SiON). Alternatively, the first passivationfilm PV1 may be made of SiO₂ or silicon nitride (SiN).

The first passivation film PV1 has therein an opening OP2. The openingOP2 is placed at a position overlapping with the opening OP1. This meansthat the wiring layer WL1 is exposed from the first passivation film PV1via the opening OP1 and the opening OP2.

The second passivation film PV2 is placed to cover the wiring layer WL1and the first passivation film PV1. The second passivation film PV2 ismade of an insulating and photosensitive resin material. The resinmaterial configuring the second passivation film PV2 is preferably apolyimide.

The second passivation film PV2 has therein an opening OP3. The openingOP3 is arranged at a position overlapping with the opening OP1 and theopening OP2. From another point of view, the wiring layer WL1 is exposedfrom the second passivation film PV2 via the opening OP1, the openingOP2, and the opening OP3.

The plating film PL1 is placed in the opening OP1, the opening OP2, andthe opening OP3. In other words, the plating film PL1 is placed on thewiring layer WL1 exposed from the opening OP1, the opening OP2, and theopening OP3.

The plating film PL1 is preferably an electroless plating film. The term“electroless plating film” as used herein means a plating film to beformed by electroless plating. The plating film PL1 is an electrolessplating film containing, for example, nickel (Ni). The plating film PL1may be an electroless plating containing gold (Au). The plating film PL1may be an electroless plating film containing palladium (Pd). Theplating film PL1 may also be a film obtained by stacking two or more ofthese electroless plating films.

The wiring layer WL1 and the plating film PL1 placed on the wiring layerWL1 configure the source pad SP.

The wiring layer WL2 is a gate wiring. As shown in FIGS. 4 and 5, thewiring layer WL2 has a surface covered with an oxide film OX. The wiringlayer WL2 is preferably made of the same material as that of the wiringlayer WL1. In crystal grains at the surface of the wiring layer WL2, aproportion of those having crystal orientation deviated by 5° or lessfrom the <111> plane is preferably 40% or more. The wiring layer WL2 iscovered with the first passivation film PV1 and the second passivationfilm PV2. The wiring layer WL2 is exposed from an opening OP4 providedin the oxide film OX, an opening OP5 provided in the first passivationfilm PV1, and an opening OP6 provided in the second passivation filmPV2.

The wiring layer WL2 exposed from the opening OP4, the opening OP5, andthe opening OP6 has a plating film PL2 thereon. The plating film PL2 ispreferably an electroless plating film. The plating film PL2 is, forexample, a Ni-containing electroless plating film. The plating film PL2may be an Au-containing electroless plating film. The plating film PL2may be a Pd-containing electroless plating film. The plating film PL2may also be a stack of two or more of these electroless plating films.

The wiring layer WL2 and the plating film PL2 placed on the wiring layerWL2 configure the gate pad GP.

A method of manufacturing the semiconductor device of First Embodimentwill hereinafter be described.

As shown in FIG. 6, the method of manufacturing the semiconductor deviceof First Embodiment has a front end step S1 and a back end step S2. Theback end step S2 has an interlayer insulating film formation step S21, acontact plug formation step S22, a wiring layer formation step S23, afirst passivation film formation step S24, a first opening formationstep S25, a second opening formation step S26, a second passivation filmformation step S27, and a plating film formation step S28.

As shown in FIGS. 7 and 8, in the front end step S1, a trench gate typepower MOSFET is formed. More specifically, firstly, epitaxial growth ofa drift region DRI is performed on a semiconductor substrate SUB havinga drain region DRA. Secondly, a body region BR and a source region SRare formed by ion implantation into the semiconductor substrate SUB.

Thirdly, a trench TR is formed in a first surface FS of thesemiconductor substrate SUB by anisotropic etching such as RIE (reactiveion etching). Fourthly, a gate insulating film GO is formed by thermaloxidation of the first surface FS of the semiconductor substrate SUB.

Fifthly, a gate electrode GE is formed by filling the trench TR, havingon the bottom wall and side wall thereof the gate insulating film GO,with a material configuring the gate electrode GE. Filling of the trenchTR with the material configuring the gate electrode GE is performed byforming a film on the first surface of the semiconductor substrate SUBwith a material configuring the gate electrode GE by CVD (chemical vapordeposition) or the like and removing a portion of the materialconfiguring the gate electrode GE protruded from the trench TR by CMP(chemical mechanical polishing) or the like.

As shown in FIGS. 9 and 10, in the interlayer insulating film formationstep S21, an interlayer insulating film ILD is formed. In forming theinterlayer insulating film ILD, firstly, a film is formed by CVD or thelike on the first surface FS of the semiconductor substrate SUB by usinga material configuring the interlayer insulating film ILD. Secondly, thefilm formed using the material configuring the interlayer insulatingfilm ILD is planarized by CVD or the like.

As shown in FIGS. 11 and 12, in the contact plug formation step S22, acontact plug CP is formed. In forming the contact plug CP, firstly, acontact hole CH is formed by anisotropic etching such as RIE.

In forming the contact plug CP, secondly, the contact hole CH is filledwith the material configuring a contact plug CP by CVD or the like.Thirdly, a portion of the material configuring a contact plug CPprotruded from the contact hole CH is removed, for example, by etchback. Removal of the portion of the material configuring a contact plugCP protruded from the contact hole CH may be performed by CMP.

As shown in FIGS. 13 and 14, in the wiring layer formation step S23, awiring layer WL1 and a wiring layer WL2 are formed. In forming thewiring layer WL1 and the wiring layer WL2, firstly, films are formed onthe interlayer insulating film ILD by using materials configuring thewiring layer WL1 and the wiring layer WL2 by sputtering or the like,respectively. This sputtering is performed preferably at a temperatureof 150° C. or more.

In forming the wiring layer WL1 and the wiring layer WL2, secondly, thefilms formed using the materials configuring the wiring layer WL1 andthe wiring layer WL2 are patterned, respectively, by photolithography,etching and the like. By ashing (ashing treatment) of a photoresist filmused for photolithography and etching, the surface of the patternedwiring layer WL1 and wiring layer WL2 is oxidized. As a result, an oxidefilm OX covering the surface of the wiring layer WL1 and the wiringlayer WL2 is formed.

As shown in FIGS. 15 and 16, in the first passivation film formationstep S24, a first passivation film PV1 is formed to cover the wiringlayer WL1 and the wiring layer WL2. Formation of the first passivationfilm PV1 is performed by CVD or the like.

As shown in FIGS. 17 and 18, in the first opening formation step S25, anopening OP2 and an opening OP5 are formed. Formation of the opening OP2and the opening OP5 is performed by partially removing the firstpassivation film PV1, for example, by photolithography and etching.After the first opening formation step S25, the oxide film OX is exposedfrom the opening OP2 and the opening OP5.

As shown in FIGS. 19 and 20, in the second opening formation step S26,an opening OP1 and an opening OP4 are formed. Formation of the openingOP1 and the opening OP4 is performed by dry etching. This dry etching ispreferably anisotropic dry etching. More specifically, the secondopening formation step S26 is performed, for example, by partiallyremoving the oxide film OX by RIE or the like with the first passivationfilm PV1 as a mask. Anisotropic dry etching for forming the opening OP1and the opening OP4 (for partially removing the oxide film OX) isperformed preferably for 20 minutes or more to 40 minutes or less. Afterthe second opening formation step S26, the wiring layer WL1 is exposedfrom the opening OP1 and the opening OP2 and the wiring layer WL2 isexposed from the opening OP3 and opening OP4.

As shown in FIGS. 21 and 22, in the second passivation film formationstep S27, a second passivation film PV2 is formed. In forming the secondpassivation film PV2, firstly, a resin material configuring the secondpassivation film PV2 is applied so as to cover therewith the wiringlayer WL1, the wiring layer WL2, and the first passivation film PV1.

Secondly, the resin material configuring the second passivation film PV2which has been applied is patterned. This patterning is performed, forexample, by photolithography to form an opening OP3 and an opening OP6.For the formation of the opening OP3 and the opening OP6, usable is notonly photolithography but also any method capable of forming the openingOP3 and the opening OP6 without leaving a residue, which will be anobstacle for a plating film PL1 and a plating film PL2, on the surfaceof the wiring layer WL1 and the wiring layer WL2 during formation of theopening OP3 and the opening OP6. Thirdly, the resin material configuringthe second passivation film PV2 thus patterned is baked. As a result,the second passivation film PV2 provided with the opening OP3 and theopening OP6 is formed.

In the plating film formation step S28, a plating film PL1 and a platingfilm PL2 are formed. Formation of the plating film PL1 and the platingfilm PL2 is performed, for example, by electroless plating. Morespecifically, firstly, the surface of the wiring layer WL1 exposed fromthe opening OP1, the opening OP2, and the opening OP3 and the surface ofthe wiring layer WL2 exposed from the opening OP4, the opening OP5, andthe opening OP6 are subjected to pretreatment.

This pretreatment includes, for example, cleaning treatment of thesurface of the wiring layer WL1 and the wiring layer WL2 by argon(Ar)-containing plasma and zincate treatment of the surface of thewiring layer WL1 and the wiring layer WL2.

Secondly, the plating film PL1 and the plating film PL2 are grown. Forthe growth of the plating film PL1 and the plating film PL2, thesemiconductor substrate SUB is immersed in a plating solution containinga material configuring the plating film PL1 and the plating film PL2. Bythe above-described steps, the semiconductor device having the structureshown in FIGS. 2 to 5 is manufactured.

Advantage of Method of Manufacturing Semiconductor Device of FirstEmbodiment

The advantage of the method of manufacturing the semiconductor device ofFirst Embodiment will hereinafter be described.

The second opening formation step S26 is performed by dry etching. Whenthe second opening formation step S26 is performed after the secondpassivation film formation step S27, carbon (C) in the secondpassivation film PV2 is sputtered by Ar or the like contained in theetching gas. The carbon thus sputtered is redeposited on the surface ofthe wiring layer W1 and the wiring layer WL2 and may hinder the growthof the plating film PL1 and the plating film PL2.

When the second opening formation step S26 is performed after the secondthe passivation film formation step S27, the surface of the secondpassivation film PV2 may be graphitized by an etching gas. As the resultof graphitization, the second passivation film PV2 may fail to functionas a passivation film because of having conductivity.

In the method of manufacturing the semiconductor device of FirstEmbodiment, on the other hand, the second opening formation step S26 isperformed prior to the second passivation film formation step S27. Atthe time when the second opening formation step S26 is performed,therefore, the second passivation film PV2 has not yet been formed andthe problem as described above therefore does not occur. According tothe method of manufacturing the semiconductor device of FirstEmbodiment, therefore, the plating film PL1 and the plating film PL2 canbe grown smoothly on the wiring layer WL1 and the wiring layer WL2,respectively, and adhesion between the wiring layer WL1 and the platingfilm PL1 and that between the wiring layer WL2 and the plating film PL2can be improved.

When the wiring layer WL1 and the wiring layer WL2 are formed bysputtering at a temperature of 150° C. or more, the appearance of thesemiconductor device in plan view (viewed from a direction orthogonal tothe first surface FS) becomes more uniform. This makes it possible tosuppress error detection at the time of a visual test of thesemiconductor device by using an image processor.

In addition, the contact plug CP is, in the vicinity of the center onthe other end side thereof, recessed toward the side of the one end.This tendency is more marked when etch back is performed in the contactplug formation step S22. Formation of the wiring layer WL1 and thewiring layer WL2 by sputtering at a temperature of 150° C. or moreimproves coverage of the recess. In this case, therefore, couplingfailure between the contact plug CP and the wiring layer WL1 or thewiring layer WL2 can be reduced.

According to the finding of the present inventors, on the other hand,when the wiring layer WL1 and the wiring layer WL2 are formed bysputtering at a temperature of 150° C. or more, a proportion, in crystalgrains at the surface of the wiring layer WL1 and the wiring layer WL2,of those having a crystal orientation deviated by within 5° from the<111> plane becomes 40% or more. An oxide film OX is grown easily on thecrystal grains having a crystal orientation deviated slightly from the<111> plane.

Table 1 shows the relationship between the time of anisotropic dryetching performed in the second opening formation step S26 and defectoccurrence (%) of the plating film PL1 and the plating film PL2.

TABLE 1 Sputtering temperature Etching time (min) Defect occurrence (%)150° C. or more 20 0.1 30 0.1 40 0.5 0 74.4

As shown in Table 1, in Samples 1 to 4, the wiring layer WL1 and thewiring layer WL2 were formed by sputtering at 150° C. or more.

In Sample 1, the anisotropic dry etching time performed in the secondopening formation step S26 was set at 20 minutes. In Sample 2, theanisotropic dry etching time performed in the second opening formationstep S26 was set at 30 minutes. In Sample 3, the anisotropic dry etchingtime performed in the second opening formation step S26 was set at 40minutes. In Sample 4, the second opening formation step S26 was notperformed.

The defect occurrence of the plating film PL1 and the plating film PL2was determined by dividing the number of semiconductor devices found tohave any growth failure in the plating film PL1 and the plating film PL2by the total number of semiconductor devices to be measured. Thepresence or absence of the growth failure was detected by observing theplating film PL1 and the plating film PL2 under an optical microscopefrom a direction perpendicular to the first surface FS.

In Samples 1 to 3, the defect occurrence of the plating film PL1 and theplating film PL2 was 0.5% or less. On the other hand, in Sample 4, thedefect occurrence of the plating film PL1 and the plating film PL2 was74.4%.

Thus, according to the method of manufacturing the semiconductor deviceof First Embodiment, it is experimentally shown that even if the wiringlayer WL1 and the wiring layer WL2 are formed by sputtering at atemperature of 150° C. or more, the plating film PL1 and the platingfilm PL2 can be grown smoothly.

From another point of view, it is experimentally shown that according tothe method of manufacturing the semiconductor device of FirstEmbodiment, the plating film PL1 and the plating film PL2 can be grownsmoothly even if a proportion, in crystal grains at the surface of thewiring layer WL1 and the wiring layer WL2, of those having crystalorientation deviated by within 5° from the <111> plane is 40% or more.

In the semiconductor device of First Embodiment, when the thickness T is1 μm or more, the wiring layer WL1 and the wiring layer WL2 can havereduced electrical resistance.

In the semiconductor device of First Embodiment, when the openings OP1and OP4 are formed with the first passivation film PV1 (meaning, aninsulating inorganic material) as a mask, ashing of a photoresist is notnecessary at the time of formation of the openings OP1 and OP4. In thiscase, therefore, it is possible to prevent re-oxidation of the surfaceof the wiring layer WL1 exposed from the opening OP1 and the wiringlayer WL2 exposed from the opening 4.

Second Embodiment

Second Embodiment will next be described. Difference from FirstEmbodiment will hereinafter be described mainly and overlappingdescription will be omitted.

A semiconductor device of Second Embodiment has a semiconductorsubstrate SUB, a gate insulating film GO, a gate electrode GE, aninterlayer insulating film ILD, a contact plug CP, a wiring layer WL1, awiring layer WL2, a first passivation film PV1, a second passivationfilm PV2, a plating film PL1, and a plating film PL2. The configurationof the semiconductor device of Second Embodiment is similar to that ofthe semiconductor device of First Embodiment in the above-describedpoints.

The configuration of the semiconductor device of Second Embodiment ishowever different from that of the semiconductor device of FirstEmbodiment in details of the wiring layer WL1 and the wiring layer WL2.

More specifically, in the semiconductor device of Second Embodiment, aproportion, in the crystal grains at the surface of the wiring layer WL1and the wiring layer WL2, of those having crystal orientation deviatedby 5° or more from the <111> plane is 70% or more.

A method of manufacturing the semiconductor device of Second Embodimenthas a front end step S1 and a back end step S2. The back end step S2 hasan interlayer insulating film formation step S21, a contact plugformation step S22, a wiring layer formation step S23, a firstpassivation film formation step S24, a first opening formation step S25,a second opening formation step S26, a second passivation film formationstep S27, and a plating film formation step S28. The method ofmanufacturing the semiconductor device of Second Embodiment is similarto that of First Embodiment in the above-described points.

The method of manufacturing the semiconductor device of SecondEmbodiment is however different from that of First Embodiment in detailsof the wiring layer formation step S23. More specifically, in the methodof manufacturing the semiconductor device of Second Embodiment, thewiring layer WL1 and the wiring layer WL2 are formed by sputtering at atemperature less than 150° C.

As shown in FIG. 24, according to the finding of the present inventors,when the wiring layer WL1 and the wiring layer WL2 are formed bysputtering at a temperature less than 150° C., a proportion, in thecrystal grains at the surface of the wiring layer WL1 and the wiringlayer WL2, of those having crystal orientation deviated by 5° or morefrom the <111> plane becomes 70% or more. An oxide film OX is hard togrow on the crystal grains having crystal orientation deviated largelyfrom the <111> plane. The method of manufacturing the semiconductordevice of Second Embodiment therefore can shorten the anisotropicetching time in the second opening formation step S26.

Table 1 shows the relationship between the sputtering temperature forforming the wiring layer WL1 and the wiring layer WL2 and defectoccurrence (%) of the plating film PL1 and the plating film PL2,respectively.

TABLE 2 Sputtering temperature Etching time (min) Defect occurrence (%)Less than 150° C. 7 5.3 150° C. or more 32.4

As shown in Table 2, the wiring layer WL1 and the wiring layer WL2 inSample 5 were formed by sputtering at a temperature less than 150° C. Onthe other hand, the wiring layer WL1 and the wiring layer WL2 in Sample6 were formed by sputtering at a temperature of 150° C. or more. Both inSample 5 and Sample 6, anisotropic dry etching time in the secondopening formation step S26 was set at 7 minutes.

In Sample 5, the defect occurrence of the plating film PL1 and theplating film PL2 was 5.3%. In Sample 6, the defect occurrence of theplating film PL1 and the plating film PL2 was 32.4%. When they arecompared while setting the etching time of these samples equal to eachother, the defect occurrence of the plating film PL1 and the platingfilm PL2 formed by sputtering at less than 150° C. becomes smallerdrastically. Thus, it has also been confirmed experimentally that themethod of manufacturing the semiconductor device of Second Embodimentcan shorten the anisotropic etching time in the second opening formationstep S26.

The invention made by the present inventors has so far been describedspecifically based on embodiments. It is needless to say that theinvention is not limited to or by these embodiments but can be changedin various ways without departing from the gist of the invention.

What is claimed is:
 1. A method of manufacturing a semiconductor devicecomprising: forming a wiring layer having a surface covered with anoxide film over a semiconductor substrate; removing a portion of theoxide film by dry etching to form, in the oxide film, a first openingfor exposing a portion of the wiring layer; forming a passivation filmcovering the wiring layer, provided with a second opening communicatedwith the first opening, and comprising an insulating resin material; andgrowing a plating film over the wiring layer exposed from the firstopening and the second opening.
 2. The method of manufacturing asemiconductor device according to claim 1, wherein the resin material isphotosensitive, and wherein the second opening is formed byphotolithography.
 3. The method of manufacturing a semiconductor deviceaccording to claim 2, wherein the resin material is a polyimide.
 4. Themethod of manufacturing a semiconductor device according to claim 1,wherein the wiring layer is formed by sputtering at a temperature of150° C. or more.
 5. The method of manufacturing a semiconductor deviceaccording to claim 4, further comprising: forming an interlayerinsulating film provided with a contact hole over the semiconductorsubstrate; and forming, in the contact hole, a contact plug electricallycoupling the wiring layer to the semiconductor substrate, wherein theforming the contact plug comprises removing a contact plug configuringmaterial protruded from the contact hole.
 6. The method of manufacturinga semiconductor device according to claim 5, wherein the removing acontact plug configuring material protruded from the contact hole isperformed by etch back.
 7. The method of manufacturing a semiconductordevice according to claim 4, wherein a proportion, in crystal grains atthe surface of the wiring layer, of those having crystal orientationdeviated by 5° or less from a <111> plane is 40% or more.
 8. The methodof manufacturing a semiconductor device according to claim 4, whereinthe dry etching is performed for 20 minutes or more to 40 minutes orless.
 9. The method of manufacturing a semiconductor device according toclaim 1, wherein a proportion, in crystal grains at the surface of thewiring layer, of those having crystal orientation deviated by 5° or lessfrom a <111> plane is 70% or more.
 10. The method of manufacturing asemiconductor device according to claim 1, wherein the wiring layer hasa thickness of 1 μm or more.
 11. The method of manufacturing asemiconductor device according to claim 1, wherein the plating film isan electroless plating film.
 12. The method of manufacturing asemiconductor device according to claim 1, wherein the plating film isan electroless nickel plating film.
 13. The method of manufacturing asemiconductor device according to claim 1, wherein the first opening isformed by etching with an insulating film comprised of an inorganicmaterial as a mask.